发明名称 PACKET MULTIPLEXER
摘要 <p>PURPOSE: To allow the packet multiplexer to employ a memory and a memory control section at a low speed inexpensively. CONSTITUTION: A memory control section 112-1 receives data of a line number to be registered and writes the data to a memory 111-1 and reads the data commanded by a packet multiplexer control section 12 from the memory 111-1 and writes the data to a packet standby buffer 113-1. In this case, the packet multiplexer control section controls the data of a line number to be written in the packet standby buffer 113-1 by one packet length. The packet multiplexer control section gives data to a selector 13 from any of packet generating sections 11-1-11-m by one packet length to allow an output of the selector 13 to be an output of the packet multiplexer.</p>
申请公布号 JPH08195773(A) 申请公布日期 1996.07.30
申请号 JP19950006180 申请日期 1995.01.19
申请人 HITACHI LTD;HITACHI COMMUN SYST INC 发明人 MURAKAMI MASARU;ASHI MASAHIRO;SHIMIZU KAZUHIRO;YAMAMOTO NOBUYUKI
分类号 H04L12/56;(IPC1-7):H04L12/56 主分类号 H04L12/56
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