| 摘要 |
PURPOSE: To improve the use efficiency of a ROM for writing an instruction code and to accelerate fetch speed. CONSTITUTION: Instruction data QA and QB of respective one byte for each of two continuous addresses of program counter values PC and PC+1 are successively read from a ROM 3A through an address translator 13 and written through a switch 12 and a switch circuit 14 to the designated areas of write pointers WP and WP+1 at an instruction register(IR) 4B where the unit registers of 8 bits are arranged in 4 columns×five rows. The arrangement of instruction data becomes the order of this read inside the rows but the bytes of the arrengement of instruction data inside these rows are successively shifted one by one in the arranging order of rows. For example in the figure, a maximum instruction length is defined as four bytes, data for one row are extracted from the row that is designated by the read pointer of the IR 4B, namely, from the row in which the instruction data for one instruction code are first arranged from the head (left edge column) to a decoder 11 and when it is decided by a deciding circuit 17 that the decoding of the instruction code is valid in this case, the execution of that instruction is started.
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