| 摘要 |
<p>PROBLEM TO BE SOLVED: To provide a smart card for reducing the burdens of a CPU by performing a parity inspection in an input/output device. SOLUTION: A second register 32 reads the data of a data bus and performs output from parallel detection terminals CD0-CD7 to a parity operation part 34 at the time of transmission. A parity bit DPB generated in the parity operation part 34 is read to a first register 31. Then, first - third registers 31-33 perform shift output corresponding to shift clocks SCK and serial data are transmitted from the input/output terminal SIO of the card. At the time of reception, the first - third registers 31-33 shift-input reception data corresponding to the shift clocks SCK, and at the time, the reception data are inputted from the parallel detection terminals CD0-CD7 of the second register 32 to the parity operation part 34. Then, the parity bit RPB by the first register 31 and the parity bit DPB of an arithmetic result by the parity operation part 34 are inspected in a parity detection part 35.</p> |
