发明名称 |
Cache memory system employing virtual address primary instruction and data caches and physical address secondary cache |
摘要 |
A two-level cache memory system for use in a computer system including two primary cache memories, one for storing instruction and one for storing data. The system also includes a secondary cache memory for storing both instructions and data. The primary and secondary caches each employ their own separate tag directory. The primary caches use a virtual addressing scheme employing both virtual tags and virtual addresses. The secondary cache employs a hybrid addressing scheme which uses virtual tags and partial physical addresses. The primary and secondary caches operate in parallel unless the larger and slower secondary cache is busy performing a previous operation. Only if a "miss" is encountered in both the primary and secondary caches does the system processor access the main memory.
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申请公布号 |
US5542062(A) |
申请公布日期 |
1996.07.30 |
申请号 |
US19930172684 |
申请日期 |
1993.12.22 |
申请人 |
SILICON GRAPHICS, INC. |
发明人 |
TAYLOR, GEORGE S.;FARMWALD, P. MICHAEL;LAYMAN, TIMOTHY P.;NGO, HUY X.;ROBERTS, ALLEN W. |
分类号 |
G06F12/08;G06F12/10;(IPC1-7):G06F12/08 |
主分类号 |
G06F12/08 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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