| 摘要 |
PURPOSE: To provide a clock pulse regenerating circuit which obtains a clock with arbitrary duty. CONSTITUTION: A D-type FF 2 inputs an input clock signal as its clock input from an input terminal 1 and inputs an H level as its data input, and a D-type FF 6 inputs the input signal as its clock input from the input terminal 1 and an H level as its data input. Then a delay circuit 3 inputs the output of the D-type FF 2 and inputs the output to the reset input of the D-type FF 2, and a delay circuit 4 inputs the output of the D-type FF 2 and outputs an output clock signal from the D-type FF 6 to an output terminal 5 as the reset input of a D-type FF 6. Further, the delay circuit 3 inputs the output of the D-type FF 2 and inputs the output to the reset input of the D-type FF 2, and the delay circuit 4 inputs the output of the delay circuit 3 and outputs an output clock signal from the D-type FF 6 to the output terminal 5 as the reset input of the D-type FF 6. |
