| 摘要 |
A latch circuit includes a plurality of transistors, a set input for receiving a set signal coupled to a first transistor of the plurality of transistors, a reset input for receiving a reset signal coupled to a second transistor of the plurality of transistors, a third transistor of the plurality of transistors coupled to the first transistor and a fourth transistor of the plurality of transistors coupled to the first transistor, a fifth transistor of the plurality of transistors coupled to the second transistor, a sixth transistor of the plurality of transistors coupled to the second transistor, and a node coupled to an output device, the fourth transistor and the sixth transistor. A first feedback loop includes an inverter, the output device, the node and the fourth transistor. A second feedback loop includes the inverter, the output device, the node and the sixth transistor. The first feedback loop continuously outputs a first signal and the second feedback loop continuously outputs a second signal. The first transistor enables the first feedback loop and disables the second feedback loop when the second feedback loop is outputting the second signal and the set signal changes from a first state to a second state and the second transistor enables the second feedback loop and disables the first feedback loop when the first feedback loop is outputting the first signal and the reset signal changes from the second state to the first state.
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