发明名称 |
Circuit for freezing the data in an interface buffer |
摘要 |
A circuit for enabling data transfer between one data bus connected to a number of devices, such as accelerator cards, and a second data bus, such as one found in a computer. The two data busses are connected by a number of FIFO buffers, and an arbitrator selects a source and destination for each packet. The circuit allows the computer to freeze the data in any or all buffers so that it can be inspected and changed if necessary, but only after the entire current packet for the selected buffer or buffers has been transferred.
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申请公布号 |
US5541932(A) |
申请公布日期 |
1996.07.30 |
申请号 |
US19950383032 |
申请日期 |
1995.02.03 |
申请人 |
XEROX CORPORATION |
发明人 |
NGUYEN, UOC H.;SU, SAM;CHEUNG, LI-FUNG;APOSTOL, GEORGE |
分类号 |
G06F13/40;G06F13/42;(IPC1-7):H04L12/40 |
主分类号 |
G06F13/40 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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