PHASE REGULATING CIRCUIT

摘要

a clock generator (10) for generating four clocks having 90 degrees of phase difference one another and having the same velocity of an input data by use of a clock having double frequency of the input data; a data latching section (11) for latching the input data; a data shift detector (12) for detecting the shift of the input data; an output stabilizer section (13) for maintaining the final output data and clock of the shift detector (12) to have a stabilized phase relationship; and an output selector (14) for selectively outputting one of the output data from the data latching section (11) under the control of the output of the output stabilizer section (13), thereby selectively outputting one of the outputs from the clock generator (10).