Memory cell wiring circuit

摘要

The circuit includes two memory units (21a,21b), two word readout lines (182a,182b), a bit readout line (192), and a read buffer units (224a). Each memory unit is formed from a flip-flop element to store data, with each of the output terminals (201a-201d) of the inverter units (14a-14d) connected to the input of the other inverter unit. The buffer is controlled by the word readout line to receive respective inputs from the two memory cells and to output data to the bit line. The data is input to each buffer via respective logic circuits (16) having an AND gate receiving respective memory unit inputs and word readout line inputs. The AND gate outputs are connected to a single NOR gate. The buffer signals are output via respective parallel transistor assemblies (130-139) also under control of the word readout lines.