LOGIC ANALIZER APPARATUS FOR DUO-BINARY SIGNAL

摘要

two comparative operators (1) for comparing n input signals simultaneously received from each channel with a reference voltage; a memorizing start-up condition detector (5) for comparing the two output signals from the comparative operators (1) with a predetermined memorizing start-up condition to generate a memorizing start-up signal; a sample/hold means (2) for regulating the output of the comparative operators (1) in accord with the predetermined memorizing start-up condition; a code and logic determining means (4) for determining the code and logic; a memory (6) for storing the duo-binary-signals of each channel; and a display (7) for displaying the signal stored in the memory (6).