| 摘要 |
a contact point to the drain of pull-up PMOS(PM51) by commonly connecting the source of the PMOS(PM52),(PM53); the drain of the PMOS(PM52) and the gate of PMOS(PM53) by NMOS(NM55) where a gate port is controlled by equalizer signal(EQ1); the gate and drain of the PMOS(PM52),(PM53) to the source and drain of NMOS(NM53),(NM56) where the gate port is controlled by equalizer signal(EQ2); the drain of the PMOS(PM52),(PM53) through the NMOS(NM55),(NM56) where the gate port is controlled by the equalizer signal(EQ1),(EQ2); the gate and drain of the PMON(PM52),(PM53) to the gate and drain of NMOS(NM57),(NM58); the source of the NMOS(NM57),(NM58) to the drain and source of NMOS(NM61) where the gate port is controlled by equalizer signal(EQ3); an inner voltage port(VA) to the source of NMOS(NM62),(NM63) commonly in addition to connecting the source of the NMOS(NM57),(NM58) to the drain of NMOS(NM62),(NM63) where the gate port is controlled by noise control signal(SNA),(SNB); the source of the NMOS(NM61) to the drain of pull-down NMOS(NM64).
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