发明名称 Methods providing oxide layers having reduced thicknesses at central portions thereof
摘要 Methods of forming an integrated circuit device may include forming first and second spaced apart source/drain regions on a surface of a semiconductor substrate. A gate insulating layer can be formed on the semiconductor substrate extending between the first and second spaced apart souce/drain regions. The gate insulating layer can have a reduced thickness at a central portion thereof between the first and second spaced apart source/drain regions. A thickness of the gate insulating layer can increase as it extends toward each of the source/drain regions. A gate electrode can be formed on the gate insulating layer such that the gate insulating layer is between the semiconductor substrate and the gate electrode. Related devices are also discussed.
申请公布号 US6969658(B2) 申请公布日期 2005.11.29
申请号 US20020173373 申请日期 2002.06.17
申请人 SAMSUNG ELECTRONICS CO., LTD. 发明人 CHO CHANG-HYUN;CHO MIN-HEE;KIM KI-NAM
分类号 H01L21/28;H01L21/8234;H01L21/8242;H01L27/088;H01L27/108;H01L29/423;(IPC1-7):H01L21/823 主分类号 H01L21/28
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