发明名称
摘要 <p>PURPOSE:To prevent a defect in operation on a main storage device, etc., even if a CPU is replaced and the frequency of a clock is varied by including both OUT and IN pulses in operation pulses of a computer, and altering them and leaving a time between oscillations of both the pulses. CONSTITUTION:The input terminal A of a pulse modulating circuit system 2 is connected to the pulse oscillating circuit 1 that the personal computer originally has and when a pulse train that the clock oscillates is inputted to the input terminal A, a modulated pulse train is outputted from the output terminal B. This pulse train consists of pulses twice as many as those of the clock and a long pulse interval and a short pulse interval are alternated. Namely, the CPU reads data out of a main memory 3 at a pulse rise after the short pulse interval and writes data in the memory 3 at a rise after the long pulse interval. The interval from the reading to the writing of the memory 3 is longer than pulse intervals in the modulated pulse train. The pulse intervals are a half as long as the original intervals and the number of operations is twice.</p>
申请公布号 JP2516548(B2) 申请公布日期 1996.07.24
申请号 JP19930090299 申请日期 1993.04.16
申请人 FUKUI DENKI SANGYO KK 发明人 TAKEUCHI HIROFUMI
分类号 G06F1/04;G06F1/06;G06F1/12;(IPC1-7):G06F1/04 主分类号 G06F1/04
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