DRAM data transfer system

摘要

A data transfer system for DRAM operates in a burst transfer mode, wherein the OE line is employed to start the burst transfer mode with change of its potential as a start signal. The burst transfer toggles CAS or RAS to synchronize it with data output as if it were a clock signal. This eliminates the necessity to uniquely provide a clock circuit for the DRAM. In addition, OE maintains the function as a switch for determining whether or not data can be output as in the background art by switching the operation mode from the burst transfer mode. Thus, it maintains high compatibility with the conventional DRAM transfer system. <IMAGE>