IMAGE PROCESSING CIRCUIT OF FACSIMILE

摘要

an address decoder(2) for designating the start address of binary pattern or multi-step according to image processing information outputted from a CPU(1), a register block(3) for storing the binary pattern and pattern; a document background color correcting unit(4); a binary/multi-step switch(5) for selectively outputting voltages distributed by predetermined resistors(R1,R2); a D/A converter(6) for converting the digital signal stored in and outputted from the register block(30) into an analog signal, a current/voltage converter(7) converting the analog signal into voltage source, and a comparator(8) for comparing the voltage outputted from the current/voltage converter(7) with its analog image output to output a digitalized image.