| 摘要 |
PCT No. PCT/SE95/01209 Sec. 371 Date Jun. 9, 1997 Sec. 102(e) Date Jun. 9, 1997 PCT Filed Oct. 17, 1995 PCT Pub. No. WO96/12226 PCT Pub. Date Apr. 25, 1996The present invention relates to a system and method respectively for processing of data comprising a central processor system comprising at least one signal processor (SPU) for processing and administrating signals and at least one executing processor (IPU) comprising a multiport process register memory (RM). The signal processor (SPU) and the executing processor (IPU) cooperate and the system further comprises a system memory (SM). At least one traffic handling program level (THL, BAL) of the system comprises at least two identical register sets in the register memory (RM) of the executing processor which comprises at least one signal input port (A), a signal output port (B) and a data access port (C). Signal data transportations between the signal processor (SPU) and the executing processor (IPU) are done by the signal processor (SPU) during execution. The execution processor (IPU) directly switches from execution of one job to another job through switching register sets. |
