发明名称 TIMING TEST UNIT
摘要 PURPOSE:To enable the test to detect defective memory cells from the first, by testing the printed board of the timing generating circuit with the printed circuit board in itself and assembling it on the main memory unit after confirming the normality.
申请公布号 JPS53104135(A) 申请公布日期 1978.09.11
申请号 JP19770018839 申请日期 1977.02.23
申请人 FUJITSU LTD 发明人 ARAYA OSAMU;HASHIMOTO MASATO
分类号 G06F11/00;G06F1/04 主分类号 G06F11/00
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