| 摘要 |
<p>A triggering circuit obviates propagation differences in differential combinatorial logic clocking of upstream and downstream state machines ("SM's"). The triggering circuit imposes an output state on the downstream SM in response to the appearance of an appropriate combination of the upstream SM output state and selected data at the triggering circuit input. The triggering circuit and the upstream SM are clocked from a common signal preventing the upstream SM from changing state before the triggering circuit produces the proper signal to impose the expected state on the downstream SM. The downstream SM takes on the correct output state in dependable correspondence with a selected upstream SM output state. In a preferred embodiment, a D flip-flop generates a triggering signal in response to a selected combination of upstream SM output state and system data. The D flip-flop triggering signal imposes a selected output state on a downstream SM through the asynchronous SET and CLEAR inputs of the downstream SM flip-flops. Because the D flip-flop and upstream SM are both clocked off the same trailing edge of the WRITE line, the upstream SM and D flip-flop change state together, preventing the upstream SM from changing state before the triggering signal is generated.</p> |
