| 摘要 |
a first delaying part for making the delay signal during a constant time by detecting the error signal first generated from digital input signal; a continuous delay reset part(3) which resets continuous delay part(2) by forming the output pulses to each error signal continuously generated; a continuous delay part(2) for making the delay signal for constant time to the final error signal by detecting the error signal continuously generated after error generation as a output pulse of the continuously delay reset part; a first logic-AND gate(4) which generates the delay signal considering the continuous error by logic-multiplying the output of the first delay part(1) and continuous delay part(2); a signal synchronizing part(5) which generates final synchronized delay signal to left, right channel separation signal; a second logic-AND gate(6) which controls dagital data input(DATA-IN) signal by the final delay signal which is the signal synchronization output; and a D/A convertor which converts the digital data into analog.
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