VOICE RESPONSE SERVICE SYSTEM

摘要

a clock receiver for receiving the first clock signal and a memory access signal; a clock generator for generating the same clock signal as the first clock signal for a test; a selector circuit for outputting either of the clock signals from the clock receiver or the clock generator; a clock divider and producer circuit for generating the second clock signal from the selected clock signal; the first latch for latching based on the second clock signal; an information data generator for generating an address data; a voice data memory; and a parallel/serial converter and SHW(Sub-High Way) selective circuit.