Circuit for compensating for potential voltage drops caused by parasitic interconnection resistance

摘要

A differential amplifier and an NMOS transistor are provided corresponding to each load circuit. A positive input and a negative input of the differential amplifier are coupled to a first ground interconnection and a second ground interconnection, respectively. When the selected load circuit operates, the potential received by this load circuit rises by interconnection resistances of the first ground interconnection. However, the potential received by the de-selected load circuit is reduced due to the operation of its corresponding differential amplifier and transistor. As a result, a rise in the potential of the de-selected circuit caused by the operation of the selected circuit will be suppressed. The differential amplifier and transistor corresponding to the selected load circuit also operate to reduce the potential of the selected circuit, thereby to suppress the rise in such potential.