发明名称 |
Asynchronous interface between parallel processor nodes |
摘要 |
An asynchronous interface enabling a processor node operating at a first clocking frequency to transfer and receive information from a communications network operating at a second clocking frequency. The asynchronous interface comprises an input synchronizer and an output synchronizer. The input synchronizer asynchronously receives a first plurality of information packets from the processor node and synchronously transfers the first plurality of information packets into the communications network. The output synchronizer, however, synchronously receives a second plurality of information packets from the communications network and asynchronously transfers the second plurality of information packets into the processor node. Both the input and output synchronizers are coupled between the communications network and the processor node.
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申请公布号 |
US5539739(A) |
申请公布日期 |
1996.07.23 |
申请号 |
US19940315284 |
申请日期 |
1994.09.29 |
申请人 |
INTEL CORPORATION |
发明人 |
DIKE, CHARLES;GATLIN, ROBERT;JEX, JERRY;PETERSON, CRAIG;SELF, KEITH;SUTTON, JIM |
分类号 |
G06F15/173;(IPC1-7):H04L7/04 |
主分类号 |
G06F15/173 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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