| 摘要 |
PURPOSE: To make the clock frequency and the bit transfer frequency coincide with each other to increase the clock regeneration speed by estimating the error between the clock frequency and the bit transfer frequency of data to control a phase locked loop without waiting for a cycle slip in a clock regeneration circuit. CONSTITUTION: All input data signal DATA is synchronized with the phase of an output clock signal CLK from a voltage controlled oscillator VCO 57 by a phase locked loop PLL 56. A frequency error estimation circuit decodes outputs of latch circuits 120 and 121 and estimates the error between the CLK frequency and the bit transfer frequency based on quantized phases of CLK and DATA for preceding transition and current transition by a frequency overs/ shorts signal output circuit 122 and controls a multiplying charge pump 228 of the PLL 56 by a phase synchronization control circuit so that they coincide with each other. Thus, the frequency pull-in speed is increased to increase the clock regeneration speed. |
