发明名称 Semiconductor process integrating source/drain stressors and interlevel dielectric layer stressors
摘要 A semiconductor fabrication process includes forming isolation structures on either side of a transistor region, forming a gate structure overlying the transistor region, removing source/drain regions to form source/drain recesses, removing portions of the isolation structures to form recessed isolation structures, and filling the source/drain recesses with a source/drain stressor such as an epitaxially formed semiconductor. A lower surface of the source/drain recess is preferably deeper than an upper surface of the recessed isolation structure by approximately 10 to 30 nm. Filling the source/drain recesses may precede or follow forming the recessed isolation structures. An ILD stressor is then deposited over the transistor region such that the ILD stressor is adjacent to sidewalls of the source/drain structure thereby coupling the ILD stressor to the source/drain stressor. The ILD stressor is preferably compressive or tensile silicon nitride and the source/drain structure is preferably silicon germanium or silicon carbon.
申请公布号 US2007202651(A1) 申请公布日期 2007.08.30
申请号 US20060361171 申请日期 2006.02.24
申请人 FREESCALE SEMICONDUCTOR, INC. 发明人 ZHANG DA;ADAMS VANCE H.;NGUYEN BICH-YEN;GRUDOWSKI PAUL A.
分类号 H01L21/336 主分类号 H01L21/336
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