| 摘要 |
a stereo data buffer(21) for, when stereo data(SD) is serially inputted in synchronization with a channel clock(CC) converting the stereo data into parallel N bit; a signal processor(22) for over-sampling a PGM signal outputted from the stereo data buffer(21) by K times according to a digital filter, converting it into a bit stream of PDM signal and outputting it through 1 bit channel; and a stereo signal divider(23) for separating left and right signals from the output signal of the stereo signal processor(22) and outputting them to left and right output terminals(25,24) respectively.
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