| 摘要 |
<p>A phase-locked loop having a phase error processor (PEP) circuit in which a phase error is provided to the PEP circuit in the form of a first pulse stream comprising pulses of a width dictated by the phase error between the incoming data and a local clock and a second pulse stream comprising pulses of a reference width. The circuit includes two integrators having outputs coupled to first and second inputs off a comparator, respectively. Switches couple the first pulse stream to the input of one integrator and the second pulse stream to the input of the other integrator during a first time window and reverse the connections during a second time window. The switches are controlled by a SWAP signal which alternates state at regular intervals. The output of the comparator is exclusive-ORed with the SWAP signal in order to invert the comparator output signal every other window so as to average any input offset error of the comparator or offset due to mismatch of the integrators evenly between the two pulse streams. The output of the exclusive-OR gate is coupled to the input of a D flip flop which is latched once per window. The output of the D flip flop is an UP/DOWN signal which controls an oscillator, which generates the local clock signal, to advance or retard the phase of the local clock in response to the condition of the UP/DOWN signal.</p> |
