摘要 |
<p>The circuit includes an asymmetric differential stage which has branches (Q1,Q2) of low and high gain which control respective branches (Q3,Q4) of a symmetrical differential stage. The quiescent current (Ii) of the asymmetric stage corresponds to the output of a signal amplitude suppression portion. The quiescent current (I1) of the symmetrical stage corresponds to the maximum amplitude of a signal supplied by one of its branches. The low and high gain branches are controlled by the input voltage and a voltage (Vb) which corresponds to the voltage at the start of the amplitude suppression portion, respectively.</p> |