| 摘要 |
A microprocessor includes a clock control system for dynamically varying the internal clock frequency of the microprocessor. The clock control system includes a delay sensing circuit coupled to a clock switching circuit. A set of tap points are distributed along a delay chain at the outputs of selected delay elements. Each tap point is coupled to a respective input line of a latch unit through a buffer unit. During operation of the processor, an external clock generator provides a clock signal to an input of the delay chain. The clock signal serially propagates through each delay element within the delay chain. As a particular rising or falling edge of the clock signal propagates through the delay chain, corresponding signal transitions sequentially appear at the tap points. The latch unit stores the signals at the delay chain tap points in response to a subsequent rising or falling edge of the external clock signal. Thus, an output of the latch unit is indicative of how far a particular edge of the clock signal propagated through the delay chain during a given period, and is thus indicative of a related delay associated with the microprocessor. A decoding circuit may be provided to decode the output of the latch unit and to provide an input to a clock switching circuit which controls the frequency of an internal clock signal to the processor core. If a high propagation delay is detected, the frequency of the internal processor clock is decreased. Likewise, if a low propagation delay is detected, the frequency of the internal clock is increased. <IMAGE> |
