| 摘要 |
A circuit analyzer and method are disclosed for generating and outputting a Padé via Lanczos (PVL) approximation of a frequency response of a circuit from input circuit parameters. A processing unit having a processor, memory, and stored programs processes the input circuit parameters, determines a block tridiagonal matrix by an iterative look-ahead Lanczos procedure, and calculates a Padé approximant from the block tridiagonal matrix, including poles, zeros, and residues. The look-ahead Lanczos procedure employs non-singular matrices to ensure numerical stability of the iterative calculation of the components of the block tridiagonal matrix. The output is an approximation of a plurality of frequencies at which any poles and zeros of the impulse response of the circuit occur. A graphical representation of the approximated frequency response is also produced, and qualitative measurements of the accuracy of the approximated poles are provided.
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