Processor

摘要

A processor with a plurality of operational pipelines for performing parallel processing which is includes an instruction processing section with a plurality of instruction processing pipelines and an instruction processing control section with a plurality of instruction processing control pipelines. The instruction processing control section has an instruction issuing control section which issues decoded instructions after adding tags representing data dependency between successive instructions and a pipe lock signal generating section which generates pipe lock signals for locking the pipelines until further processing is allowed.