发明名称 MANUFACTURING METHOD FOR TUNNEL TRANSISTOR
摘要 PURPOSE: To obtain current and voltage characteristics including clear negative resistance characteristic by forming a drain area by alloying method for shallow and heavily doped junction in low temperature process. CONSTITUTION: After MBE growth, as deep as a surface of the second semiconductive layer 4 is removed by etching with a gate area left, and a gate electrode is formed on an insulation film 6 left. Sn and Zn are vapor-deposited on a source area and a drain area, respectively. Then a GaAs surface is alloyed at 430-450 degree, so that, on the source and drain areas, the first semiconductive layer 3 consisting of degenerated n<+> -GaAs and the third semiconductive layer 5 consisting of p<+> -GaAs are formed, respectively. Lastly, by vapor deposition, a source electrode 8 and drain electrode 9 are formed. Temperature required for alloying is relatively low, so that heavily doped drain area is formed in shallow, and since diffusion of impurities in a channel area is suppressed, abrupt junction is formed, so that, the current and voltage characteristics which have clear negative resistance characteristic is obtained.
申请公布号 JPH08186271(A) 申请公布日期 1996.07.16
申请号 JP19940326944 申请日期 1994.12.28
申请人 NEC CORP 发明人 UEMURA TETSUYA
分类号 H01L29/06;H01L29/66;H01L29/80;(IPC1-7):H01L29/80 主分类号 H01L29/06
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