DESIGN LAYOUT GENERATING METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUITS

摘要

A design layout generating method for generating a design pattern of a semiconductor integrated circuit is disclosed. This method comprises modifying a first modification area extracted from a design layout by a first modifying method, and modifying a second modification area extracted from the design layout so as to include the first modification area by a second modifying method on the basis of a pattern modifying guideline calculated from at least a partial design layout in the second modification area.