发明名称 |
Dynamic semiconductor memory device |
摘要 |
A NAND-type dynamic semiconductor memory device having a folded bit architecture which reduces chip size and decreases array noise and soft error. The device is comprised of a plurality of memory cell groups, each group comprised of a plurality of bit memory cells connected in series, each bit memory cell having a MOS transistor and a capacitor. Two adjacent memory cell groups are connected respectively to one of a pair of bit lines. Each bit line is coupled respectively to a first one of the transistors located at the end of each memory cell group. A pair of first word lines are coupled respectively to the gates of the first one of the transistors coupled to the paired bit lines. A plurality of second word lines are each commonly coupled to the gates of corresponding ones of the transistors of the memory cell groups coupled to the paired bit lines.
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申请公布号 |
US5537347(A) |
申请公布日期 |
1996.07.16 |
申请号 |
US19940297957 |
申请日期 |
1994.08.31 |
申请人 |
KABUSHIKI KAISHA TOSHIBA |
发明人 |
SHIRATAKE, SHINICHIRO;TAKASHIMA, DAISABURO |
分类号 |
G11C11/401;G11C11/404;G11C11/405;H01L27/10;H01L27/108;(IPC1-7):G11C7/00 |
主分类号 |
G11C11/401 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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