发明名称 |
Exception handling circuit and method |
摘要 |
A microprocessor circuit monitors addresses generated by the microprocessor to check for various address-exception conditions. Fetch-exception status bits are generated for each instruction byte to indicate whether an address-exception was detected for each respective byte address. Once fetches are performed, the fetch-exception status bits are fed to an instruction buffer with the corresponding instruction bytes, where they are maintained until execution. Decode logic of an instruction control unit analyzes the fetch-exception status bits upon execution, and generates exceptions before the corresponding exception-causing instructions are executed. Address-exceptions occurring as the result of operand accesses are handled immediately. The operand access causing the exception is aborted, and the decode of the following instruction is modified to generate a micro-interrupt. A micro-interrupt routine determines the cause of the interrupt, and generates the appropriate exception. For breakpoint exceptions on operand accesses, the micro-interrupt routine re-executes the breakpoint-causing instruction to completion before generating the appropriate exception.
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申请公布号 |
US5537559(A) |
申请公布日期 |
1996.07.16 |
申请号 |
US19940193241 |
申请日期 |
1994.02.08 |
申请人 |
MERIDIAN SEMICONDUCTOR, INC. |
发明人 |
KANE, JAMES A.;WHITTED, III, GRAHAM B.;CHANG, HSIAO-SHIH |
分类号 |
G06F9/38;(IPC1-7):G06F9/32 |
主分类号 |
G06F9/38 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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