发明名称 STICKY BIT DETECTING CIRCUIT
摘要 PURPOSE: To speed up a computing element by providing this sticky bit detecting circuit with an exclusive OR circuit connected to 1st and 2nd input terminals, a NOR circuit connected to both the input terminals and an exclusive AND circuit connected to the output of the exclusive OR circuit and a 3rd input terminal. CONSTITUTION: The sticky bit detecting circuit consists of the input terminals (a), (b), cin, the exclusive OR circuit 6, the NOR circuit 7, the exclusive AND circuit 8, and output terminals out, cout. Namely the one-bit input sticky bit detecting circuit is provided with the circuit 7 connected to the input terminals (a), (b) and the circuit 8 connected to the output of the circuit 6 and the input terminal cin. For instance, the detecting circuit detects the OR of all bits excluding a carry bit (a+b) without executing addition (a+b) of two values (a), (b) each of which consists of (n) bits. When a computing element is constituted of the sticky bit detecting circuit, the speed of operation is increased.
申请公布号 JPH08185312(A) 申请公布日期 1996.07.16
申请号 JP19940328137 申请日期 1994.12.28
申请人 NEC CORP 发明人 HAGIWARA YASUHIKO
分类号 G06F7/38;G06F7/483 主分类号 G06F7/38
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