| 摘要 |
An input register holds, as an input operand to be square rooted, a floating-point number with an exponential radix is 2. An approximation of the reciprocal of a square root is retrieved from a table information store unit by an address composed of a least significant bit of an exponent and upper bits of a mantissa provided from the input register. The mantissa, with a leading bit appended, is normalized by a normalization circuit in units of two bits. An output of a remainder hold circuit in which a 0th remainder serves as a normalized operand is multiplied by a retrieved approximation to find a partial square root. Partial square roots found in iterative calculations are merged by a digit place alignment circuit and an adder. By making use of an inverter, a multiplicand generator, and an (R+SxT) arithmetic unit, a remainder being used in the next iterative calculation is found by subtracting a product of the merged square root times the partial square root from a remainder found in the preceding iterative calculation.
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