发明名称 Circuitry and method for clamping a boost signal
摘要 A clamping circuit clamping a boost signal supplied on a boost line includes a p-channel, MOS transistor and an n-channel MOS transistor. These MOS transistors are serially connected between an internal power supply line and the boost line. p-channel MOS transistor receives a clamping level control signal from a clamp control circuit at its gate. In accordance with the clamping level control signal a clamping level given by clamping circuit is varied. Therefore, by decreasing the clamping level of the boost line during an overvoltage-applied mode such as burn-in test, deterioration of components due to an overvoltage can be prevented.
申请公布号 US5537073(A) 申请公布日期 1996.07.16
申请号 US19950412798 申请日期 1995.03.29
申请人 MITSUBISHI DENKI KABUSHIKI KAISHA 发明人 ARIMOTO, KAZUTAMI
分类号 H03K5/08;G05F1/46;G11C5/14;G11C11/401;G11C11/407;H03K5/007;(IPC1-7):H03K3/01 主分类号 H03K5/08
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