| 摘要 |
A comparator circuit includes a differential amplifier circuit, a latch circuit, and a control signal generating circuit. The latch circuit includes a pair of cross-coupled inverting amplifiers that pull the output signals of the differential amplifier to the high and low logic levels, a control transistor that activates the latch circuit in synchronization with a clock signal, and an equalizing transistor that equalizes the output signals when the latch circuit is inactive. The equalizing transistor is switched on and off by a control signal generated from the clock signal by the control signal generating circuit. The high-level potential of the control signal is lower than the high-level potential of the clock signal. Switching noise at the control electrode of the equalizing transistor is therefore reduced, permitting high-speed operation.
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