发明名称 ARITHMETIC UNIT
摘要 PURPOSE: To provide an arithmetic unit which can suppress the undesired signal transition and the unnecessary charging and discharging caused by the glitch with the signal propagation delay difference and can reduce the power consumption. CONSTITUTION: The switch circuits 33-1 to 33-3 are provided at each input side of adders placed at the arithmetic stages ST1 to ST3 of the 1st to 3rd stages to secure the coincidence among the data transmission phases. Then the delay control circuits 4-1 to 4-3 are added to successively turn on the circuits 33-1 to 33-3 with the delay time equivalent to the processing time of each arithmetic stage. In such a constitution, the useless calculation by the undesired signal change can be eliminated and the increase of power consumption can also be prevented.
申请公布号 JPH08179932(A) 申请公布日期 1996.07.12
申请号 JP19950263227 申请日期 1995.10.11
申请人 SONY CORP 发明人 SENOO KATSUNORI;SONEDA MITSUO;NAGAI TOMOTOSHI
分类号 G06F7/527;G06F7/52;G06F7/523;G06F7/53;G06F7/533 主分类号 G06F7/527
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