发明名称 MEMORY DEVICE FOR MULTIPROCESSING SYSTEM
摘要 <p>PURPOSE: To cut off a fault part and to let a remaining computer continuously perform operations while accessing the memory module of its own system even when a fault is generated on a communication channel for connecting the computers or in the memory module by equivalently keeping the contents of the memory modules inside the respective computers at all times. CONSTITUTION: When a system bus control part 11 recognizes that a corresponding address is write or read to a memory module area, data are written or read to the corresponding address of a memory array 16 through a memory control part 13. When the access of an internal bus 12 from the system bus control part 11 and the internal bus 12 from an inter-system equivalent communication control part 17 at the time of data reception compete, competition control is performed in bus arbitration circuits 11a and 17a. In such a manner, since the equivalence of the memory modules is guaranteed, even when the computer during the operation as an operating system fails, the computer of a standby system uses only the memory module of its own system and takes over a processing.</p>
申请公布号 JPH08180030(A) 申请公布日期 1996.07.12
申请号 JP19940323095 申请日期 1994.12.26
申请人 MITSUBISHI ELECTRIC CORP 发明人 SUGITA MASANORI
分类号 G06F15/17;G06F11/20;G06F15/163;G06F15/167;(IPC1-7):G06F15/163 主分类号 G06F15/17
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