发明名称 |
TIME INFORMATION CODER-DECODER, AND CODER AND DECODER |
摘要 |
PURPOSE: To operate a PLL circuit of a decoder side correctly when a relative time interval of sent packets has an error. CONSTITUTION: A counter circuit 12 of a coder 10, a decoder 20 is actiuated by a clock from an ATM line 17 being a transmission line respectively and an interrupt signal generating circuit 13 generates a periodic interrupt signal based on the count of the counter circuit 12. A time information generating circuit 14 of the coder 10 outputs the count when the interrupt signal is received as the parameter of time information and a time information latch circuit of the decoder side applies the parameter of the time information to be latched to a PLL circuit in a timing of the interrupt signal. |
申请公布号 |
JPH08181688(A) |
申请公布日期 |
1996.07.12 |
申请号 |
JP19940337174 |
申请日期 |
1994.12.26 |
申请人 |
VICTOR CO OF JAPAN LTD |
发明人 |
YAMADA KAZUYA |
分类号 |
H04L7/033;H04L12/70;H04L12/951;H04N7/62;H04Q3/00;H04Q11/04 |
主分类号 |
H04L7/033 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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