| 摘要 |
A phase locked loop is provided to generate an internal clock with a high frequency by receiving a test clock of a low frequency in a test mode. A first clock divider unit(210) generates a second input clock by dividing a first input clock. A clock selection unit(220) outputs the first or the second input clock selectively in response to a test signal. A phase frequency detection unit(230) generates a detection signal by detecting phase difference between a feedback clock and an output clock of the clock selection unit. A control voltage generation unit(240) generates a control voltage having a voltage level corresponding to the detection signal. A voltage controlled oscillator unit(250) generates an internal clock having a frequency corresponding to the control voltage. A second clock divider unit(260) generates the feedback clock by dividing the internal clock.
|
