Erhöhungsspannungsschaltkreis zur Benutzung im aktiven Zyklus einer Halbleiterspeichervorrichtung

摘要

A boosting voltage circuit is capable of detecting a boosting voltage level in the circuit. A first circuit 20 receives a chip master clock phi R determining a stand-by state and an active state and generates a detector control signal phi DET activated after a first delay time and having a first pulse width and a latch control signal phi LAT activated after a second delay time and having a second pulse width. A second circuit 30 responds to the detector control signal phi DET and the latch control signal phi LAT and generates a detecting signal phi PD indicative of the potential of the boosting voltage. A third circuit 50 generates a boosting voltage generator control signal phi PC simultaneously activated together with the detecting signal phi DET in response to the chip master clock phi R. First and second boosting voltage generators 40, 60 respectively operate in the stand-by state and active state. In a further embodiment (Fig 13) a register (70) is connected between the boosting voltage detector 30 and the first and second boosting voltage generators 40, 60. Circuit details for the circuit blocks 20-60 are described (Figs 7-10 and 14-17). <IMAGE>