Apparatus and method for automatic sense and establishment of 5V and 3.3V operation

摘要

An interface circuit is provided for connecting to a multi-mode signal bus. The signal bus (e.g., a PCI local bus) can operate in either a first or second signaling mode. The first signaling mode is one in which discrete logic levels (e.g., binary "0" and "1") are represented by a first set of voltage levels (e.g., 0V-5V). The second signaling mode is one in which discrete logic levels are represented by a different, second set of voltage levels (e.g., 0V-3.3V). The interface circuit includes an intermediate level generator circuit for generating, from the first voltage level (5V), an intermediate voltage level (V4) between the possible voltage levels of the first and second signaling modes (V5 and V3). A comparator compares the power level of the signal bus against the intermediate voltage level (V4) and determines which signaling mode the signal bus is operating in. Configurable I/O cells of the interface circuit are then automatically configured to operate in the corresponding signaling mode (V5 or V3).