Data transfer control apparatus wherein a time value is compared to a clocked timer value with a comparison of the values causing the transfer of bus use right

摘要

To change the priority order of a DMA transfer circuit and a CPU for the bus use right in a data processing system comprising the DMA transfer circuit, when an overflow occurs in the DMA transfer timer during DMA transfer, a request signal for shifting the bus use right from the DMA transfer circuit to the CPU is outputted to a bus use right decision circuit to suspend DMA transfer. After the bus use right is transferred from the DMA transfer circuit to the CPU, the CPU resumes operation. When an overflow occurs in the DMA transfer timer, a request signal for shifting the bus use right from the CPU to the DMA transfer circuit is outputted to the bus use right decision circuit to transfer the bus use right from the CPU to the DMA transfer circuit with the same means as the start of DMA transfer and to resume DMA transfer.