MULTI BIT TEST CIRCUIT AND METHOD OF SEMICONDUCTOR MEMORY DEVICE

摘要

a multiplxer(12) for outputting a same level of logic data to multiple data buses; a 1st comparator(14) for checking logic levels of data buses; a test controller(10) for activating the multiplxer and 1st comparator complimentarily by combining a test enable signal, a read signal and an input signal; a data in/out lines for connecting data buses through read lines and an input path; 2nd comparator for comparing logic levels of data in/out lines; and a data in/out controller for connecting data in/out lines to the input path or the read lines by combining an input or a read control signal with a column address signal in a 1st operating mode, and transmitting the output of 2nd comparator to a data bus in 2nd operating mode.