| 摘要 |
<p>An integrated memory circuit is described which has a counter for producing a sequential or interleaved address sequence. The addresses produced are used to access memory elements in a Burst Extended Data Output Dynamic Random Access Memory (Burst EDO or BEDO DRAM). The address is changed in response to a rising edge of a column address signal (CAS*). The memory also includes a buffer circuit which latches the output of the address counter in response to the falling edge of the column address signal. Memory cells are accessed in a burst manner on the falling edge of the column address signal using the address latched in the buffer. The memory includes a generator circuit for generating an internal control signal based upon external column address signals. The generator circuit detects the first active transition of the column address signals and the first inactive transition of the column address signals. Outputs of the counter are compared with outputs of an input address latch to detect the end of a burst sequence and initialize the device for another burst access.</p> |
