| 摘要 |
A digital signal is interleaved by delaying samples thereof an integral number of times a unit delay ( DELTA T) in accordance with a cyclically repeated delay pattern (a1,..,aM). Select lines (AL(1)..AL(M)) of a memory (MEM) are cyclically activated (HAS) at a cycle rate equal to unit delay ( DELTA T). During the activation (HAS) of a select line (AL(1)..AL(M)), both data is written and read from the memory. The data written (IG(1,j)..IG(k,j)) comprises a relevant bit of each sample to be delayed in an integral number of sample groups. Each sample group is associated with one delay pattern cycle. The data read (b(1,1,j)@al..b(1,M,j)@aM..b(k,1,j)@al..b(k,M,j)@aM) comprises a number of bits which is equal to the number of bits written. The bits are read in accordance with the delay pattern. Accordingly, the speed requirements imposed on the memory (MEM) are relatively lax.
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