Method for identifying untestable & redundant faults in sequential logic circuits

摘要

A method of identifying redundant and untestable faults in a sequential logic circuit. A lead in the circuit is selected and the circuit is analyzed to determine which faults would be hypothetically undetectable at a given time frame if the selected circuit lead were unable to assume a logic 0 at a starting time frame, and which faults would be hypothetically undetectable at the given time frame if the selected circuit lead were unable to assume a logic 1 at the starting time frame. Faults that would be undetectable at the given time frame in both hypothetical cases are identified as redundant and untestable faults. This analysis may be repeated for each of a plurality of time frames in a range of time frames which includes the starting time frame. Faults whose detection would not be possible if the selected lead were unable to assume a given value at the starting time frame may be determined based on a sequential implication procedure comprising the propagation of uncontrollability indicators and the backward propagation of unobservability indicators. An uncontrollability indicator for the given (0 or 1) value is assigned to the selected circuit lead and is propagated through the circuit and/or through a range of time frames according to a predetermined set of propagation rules. Unobservability indicators are generated in the circuit at various time frames based on the uncontrollability indicators, and these unobservability indicators are then propagated backward through the circuit and/or backward through the range of time frames, also in accordance with a predetermined set of propagation rules. The hypothetically undetectable faults are then determined based on the resultant indicators and their corresponding circuit leads and associated time frames. <IMAGE>