发明名称 |
Threshold voltage extracting method and circuit using the same |
摘要 |
The transistor threshold extraction circuit in accordance with the present invention has an output (OT) and comprises: a) at least one first (M1) and one second (M2) transistor of the same type having respectively two control terminals (G1,G2) and having essentially the same threshold with the control terminal (G1) of said first transistor (M1) connected to a constant potential node (IT), b) a current mirror (MC) having at least one input terminal (IM) and one output terminal (OM) coupled respectively to said first (M1) and second (M2) transistors so as to supply to them the bias currents, c) a first (VDD) and a second (GND) potential reference, and d) a voltage divider (VD) having an intermediate tap (E3) and a first (E1) and a second (E2) end terminals. The control terminal (G2) of said second transistor (M2) is coupled to said tap (E3) and said divider (VD) is biased by coupling said first (E1) and second (E2) end terminals respectively to said first (VDD) and second (GND) potential references. The output (OT) is coupled to one (E1) of said end terminals. <IMAGE> |
申请公布号 |
EP0720078(A1) |
申请公布日期 |
1996.07.03 |
申请号 |
EP19940830593 |
申请日期 |
1994.12.30 |
申请人 |
CO.RI.M.ME. |
发明人 |
BRUNO, DARIO;GIACALONE, BIAGIO;MANARESI, NICOLO;FRANCHI, ELEONORA |
分类号 |
G05F3/24;G05F3/26 |
主分类号 |
G05F3/24 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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